EE W241A

Digital Integrated Circuits

CMOS devices and deep sub-micron manufacturing technology. CMOS inverters and complex gates. Modeling of interconnect wires. Optimization of designs with respect to a number of metrics: cost, reliability, performance, and power dissipation. Sequential circuits, timing considerations, and clocking approaches. Design of large system blocks, including arithmetic, interconnect, memories, and programmable logic arrays. Introduction to design methodologies, including laboratory experience.

 Estimated Workload: 12 hours/week
 Prerequisites: MAS-IC Students Only
Weekly Format:

~3 hrs lecture

~1hr discussion

~8 hrs work

Topics covered:

  • Design metrics: delay, power, cost robustness.
  • Operation and modeling of CMOS Devices
  • Device current-voltage characteristics for manual and SPICE analysis
  • Circuit simulation, SPICE
  • Static CMOS inverter: voltage-transfer characteristics
  • Advanced device parameters, process variations and scaling
  • Layout design rules
  • Layout editing, Cadence Virtuoso
  • Schematic entry, Cadence Analog Artist
  • CMOS Inverter: Dynamic behavior, equivalent resistances, propagation delay
  • MOS transistor capacitances
  • IC interconnect
  • Interconnect capacitance and resistance
  • Circuit extraction, checking
  • Standard complementary CMOS combinatorial logic gates
  • Propagation delay, capacitance, voltage dependence
  • Optimization for speed, method of logical effort
  • Standard and datapath cells, Euler diagrams
  • Ratioed logic, pseudo-NMOS logic
  • Pass-transistor logic
  • Dynamic and domino logic styles
  • Sequential logic: Flip-flops, latches, registers, multivibrators
  • Clocking and timing
  • Clock distribution, timing analysis
  • Driving interconnect, buffer design
  • Digital building blocks: Adders, multipliers, shifters
  • Memory design
  • SRAM DRAM Flash 

Will be offered in Fall 2014

64×32 SRAM block design. A large (14,000 transistor) circuit block is designed for minimum area and delay while meeting a set of defined constraints (noise margins and capacitances).